Split-gate type memory cell arrays are known. For example, U.S. Pat. No. 5,029,130, which is incorporated herein by reference for all purposes, discloses a split gate memory cell and its formation, which includes forming source and drain regions in the substrate with a channel region there between. A floating gate is disposed over and controls the conductivity of one portion of the channel region, and the control gate is disposed over and controls the conductivity of the other portion of the channel region. The control gate extends up and over the floating gate.
It is also known to form high voltage logic devices on the same wafer (substrate) as the split-gate memory cell array. FIGS. 1A-10A, 1B-10B and 1C-10C show the steps in forming high voltage logic devices (e.g. 12 volt logic devices) on the same wafer as the split gate memory cells. A semiconductor substrate 10 is masked (i.e. photo resist is deposited, selectively exposed using a mask, and selectively removed, using a photolithographic process, leaving portions of the underlying material covered by remaining photo resist while leaving other portions of the underlying material (here the substrate) exposed). The exposed substrate portions are etched away leaving trenches that are then filled with dielectric material 12 (e.g. oxide) to form isolation regions in the memory cell region 14 of the wafer (see FIG. 1A), in the NMOS logic region 16 of the wafer (see FIG. 1B) and in the PMOS logic region 18 of the wafer (see FIG. 1C), all shown after the photo resist is removed. The wafer is then masked again, but this time to cover the NMOS logic and memory cell regions 16 and 14 with photo resist 20, while leaving the PMOS logic region 18 exposed. A high voltage NWEL implant is then performed on the exposed PMOS logic region 18, as shown in FIGS. 2A, 2B and 2C. The photo resist 20 blocks the implantation from the memory cell and NMOS logic regions 14 and 16 of the wafer. The photo resist 20 is removed. The wafer is then masked to cover the PMOS logic region 18 with photo resist 22, but leaving the NMOS logic and memory cell regions 16 and 14 exposed. A high voltage PWEL implant is performed on the exposed NMOS logic and memory cell regions 16 and 14 as shown in FIGS. 3A, 3B and 3C.
After the photo resist 22 is removed, a layer of oxide 24 (FG oxide) is formed on the substrate 10, a layer of polysilicon 26 (FG poly) is formed on oxide 24, and a layer of nitride 28 (FG nitride) is formed on poly layer 24, as shown in FIGS. 4A, 4B and 4C. The wafer is masked, leaving photo resist 30 on the wafer except on selected locations of the nitride 28 which are left exposed in the memory cell region 14. The exposed nitride 28 is etched using an appropriate nitride etch to expose portions of poly layer 26, as shown in FIGS. 5A, 5B and 5C. The exposed portions of the FG poly layer 26 are oxidized using an oxidation process, forming oxide areas 32 on the FG poly 26. FIGS. 6A, 6B and 6C show the resulting structure after the photo resist 30 is removed. A nitride etch is used to remove the remaining nitride layer 28. An anisotropic poly etch is used to remove exposed portions of the poly layer 26, leaving blocks of polysilicon 26 underneath the oxide areas 32 in the memory cell region 14 (which will constitute the floating gates of the memory cells), as shown in FIGS. 7A, 7B and 7C.
An oxide layer 34 is formed over the structure. After additional masking and implant steps (logic NWEL, IO NWEL, logic PWEL, IO PWEL, LLVOX and LVOX), a layer of polysilicon is deposited over the wafer. The structure is masked leaving portions of the poly layer exposed, which are then removed by a poly etch. The remaining portions of the poly layer constitute the control gates 36a in the memory cell region 14, logic gate 36b in the NMOS logic region 16, and logic gate 36c in the PMOS logic region 18. The resulting structure is shown in FIGS. 8A, 8B and 8C (after the photo resist has been removed). The structure is masked again leaving only portions of the memory cell region between pairs of adjacent floating gate poly blocks 26 exposed by photo resist 38. An implantation is performed to form source regions 40 in the portions of the substrate between the floating gate poly blocks 36a, as shown in FIGS. 9A, 9B and 9C.
After the photo resist 38 is removed and after additional masking and implant steps (logic NLDD, IO NLDD, logic PLDD and IO PLDD), the wafer is masked again, leaving the PMOS logic and memory cell regions 18 and 14 covered by photo resist, but leaving the NMOS logic area 16 exposed. An LDD implantation is then performed on the NMOS logic region 16. The photo resist is removed. The wafer is masked again, leaving the NMOS logic and memory cell regions 16 and 14 covered by photo resist, but leaving the PMOS logic region 18 exposed. An LDD implantation is then performed on the PMOS logic region 18. After photo resist removal, the wafer is masked covering portions of the structure with photo resist but leaving the NMOS logic region 16 exposed and those portions of the memory cell region 16 adjacent the control gate poly blocks 36a exposed. An N+ implantation is used to form the source/drain regions 44 and 45 in the NMOS logic region 16 and drain regions 46 in the memory cell region 14. The photo resist is removed. The wafer is masked leaving just the PMOS logic region 18 exposed by photo resist, and a P+ implantation is used to form the source/drain regions 48 and 49 in the PMOS logic region 18.
The photo resist is removed. The process continues by forming insulation spacers 50, silicide layers 52 on the poly blocks 36a, 36b and 36c and on all the source/drain regions, and insulation layers 54-57, as shown FIGS. 10A, 10B and 10C. This back end processing includes at least two more masking steps (silicide blocking to limit silicide formation, and back end processing to create the contacts 58 through the insulation over the drain regions in the memory cell region and over the source/drain regions in the logic device regions).
The above technique produces non-volatile memory cells (each with a source 40, drain 46, floating gate 26, control gate 36a) on the same substrate as high voltage NMOS logic devices (each with a logic gate 36b, source 44 and drain 45) and high voltage PMOS logic devices (each with a logic gate 36c, source 48 and drain 49). It would be desirable to reduce the complexity and cost of manufacturing the memory cells and logic devices, including the number of masking steps used.